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Access enable bit

The access enable bit for traps on accesses to activity monitor registers is required at EL2 and EL3.

In the Cortex®‑A77 core, the AMEN[4] bit in registers ACTLR_EL2 and ACTLR_EL3 controls the activity monitor registers enable.


In the Cortex‑A77 core, the AMEN[4] bit is RES0 in ACTLR and HACTLR. Activity monitors are not implemented in AArch32.
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