The following table describes the counters that are implemented in the Cortex®‑A77 core and the mapping to fixed and programmable events.
Table C3-1 Mapping of counters to fixed events
|Activity monitor counter <n>||Event type||Event||Event number||Description|
|0||Fixed||Cycles at core frequency||
|1||Fixed||Cycles at constant frequency||
||This counter is used to replicate the generic system counter that is incremented on a constant basis, and not incremented depending on the PE frequency core.|
||Instruction architecturally executed. This counter increments for every instruction that is executed architecturally, including instructions that fail their condition code check.|
The first miss event tracks whether any external load miss is outstanding and starts counting only from a first-miss until data returns for that miss. The counter does not count for any remaining part of overlapping accesses, only counting again when the first-miss condition is re-detected.
||Instructions executing through the design which act as a hint for potential high power activity.|
|Max Power Mitigation Mechanism||
||Cores can be configured to throttle back activity, and thus, power, if a high average power threshold is met.|