You copied the Doc URL to your clipboard.

AMU events

The following table describes the counters that are implemented in the Cortex®‑A77 core and the mapping to fixed and programmable events.

Table C3-1 Mapping of counters to fixed events

Activity monitor counter <n> Event type Event Event number Description
0 Fixed Cycles at core frequency 0x11 Cycles count.
1 Fixed Cycles at constant frequency 0xEF This counter is used to replicate the generic system counter that is incremented on a constant basis, and not incremented depending on the PE frequency core.
2 Fixed Instructions retired 0x08 Instruction architecturally executed. This counter increments for every instruction that is executed architecturally, including instructions that fail their condition code check.
3 Fixed First miss 0xF0

The first miss event tracks whether any external load miss is outstanding and starts counting only from a first-miss until data returns for that miss. The counter does not count for any remaining part of overlapping accesses, only counting again when the first-miss condition is re-detected.

4 Programmable High activity 0xF1 Instructions executing through the design which act as a hint for potential high power activity.
Max Power Mitigation Mechanism 0xF2 Cores can be configured to throttle back activity, and thus, power, if a high average power threshold is met.


To program AMU counter 4, you need to program the AMEVTYPER4_EL0 register. For more information, see AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0.
Was this page helpful? Yes No