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AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0

The activity counters AMEVTYPERn_EL0 are directly accessible in the memory mapped view, where n is 0-4.

Bit field descriptions

The AMEVTYPERn_EL0 is a 32-bit register.

Figure D8-6 AMEVTYPERn_EL0 bit assignments


RES0, [31:10]
Reserved, RES0.
evtCount, bits[9:0]

The event the counter monitors might be fixed at implementation. In this case, the field is:

  • Read-only for n=0-3.
  • Read-write for n=4.

See AMU events.

Configurations
Counters might have fixed event allocation.

Traps and enables

If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.

If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.

If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.

Usage constraints

Accessing the AMEVTYPERn_EL0

To access the AMEVTYPERn_EL0:

MRS <Xt>, AMEVTYPERn_EL0 ; Read AMEVTYPERn_EL0 into Xt
MSR AMEVTYPERn_EL0, <Xt> ; Write Xt to AMEVTYPERn_EL0

Register access is encoded as follows:

Table D8-7 AMEVTYPER_EL0 encoding

op0 op1 CRn CRm op2
11 011 1111 1010 <0-4>

This register is accessible as follows:

Register EL0 EL1 EL2 EL3
AMEVTYPER0_EL0 RO RO RO RO
AMEVTYPER1_EL0 RO RO RO RO
AMEVTYPER2_EL0 RO RO RO RO
AMEVTYPER3_EL0 RO RO RO RO
AMEVTYPER4_EL0 RO RO RO RW
Traps and enables

If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.

If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.

If AMUSERENR_EL0.EN is 0, then accesses to this register from EL0 are trapped to EL1.

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