AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
The AMUSERENR_EL0 enables or disables EL0 access to the activity monitors.
Bit field descriptions
The AMUSERENR_EL0 is a 32-bit register.
This register resets to value
Figure D8-4 AMUSERENR_EL0 bit assignments
- RES0, [31:1]
- Reserved, RES0.
- EN, 
Traps EL0 accesses to the activity monitor registers to EL1. The possible values are:
0 EL0 accesses to the activity monitor registers are trapped to EL1. This is the reset value. 1 EL0 accesses to the activity monitor registers are not trapped to EL1. Software can access all activity monitor registers at EL0.
- There are no configuration notes.
- Accessing the AMUSERENR_EL0
To access the AMUSERENR_EL0:
MRS <Xt>, AMUSERENR_EL0 ; Read AMUSERENR_EL0 into Xt MSR AMUSERENR_EL0, <Xt> ; Write Xt to AMUSERENR_EL0
Register access is encoded as follows:
Table D8-5 AMUSERENR_EL0 encoding
op0 op1 CRn CRm op2 11 011 1111 1010 111
This register is accessible as follows:
EL0 EL1 EL2 EL3 RO RW RW RW
NoteAMUSERENR_EL0 is always RO at EL0 and not trapped by the EN bit.
- Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped to EL3.