DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
The DBGBCRn_EL1 holds control information for a breakpoint. Each DBGBVR_EL1 is associated with a DBGBCR_EL1 to form a Breakpoint Register Pair (BRP). DBGBVRn_EL1 is associated with DBGBCRn_EL1 to form BRPn. The range of n for DBGBCRn_EL1 is 0 to 5.
Bit field descriptions
The DBGBCRn_EL1 registers are 32-bit registers.
Figure D2-1 DBGBCRn_EL1 bit assignments
- RES0, [31:24]
- BT, [23:20]
Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This includes the meaning of the value held in the associated DBGBVRn_EL1, indicating whether it is an instruction address match or mismatch, or a Context match. It also controls whether the breakpoint is linked to another breakpoint. The possible values are:
Unlinked instruction address match.
Linked instruction address match.
Unlinked Context ID match.
Linked Context ID match.
Unlinked instruction address mismatch.
Linked instruction address mismatch.
Unlinked CONTEXTIDR_EL1 match.
Linked CONTEXTIDR_EL1 match.
Unlinked VMID match.
Linked VMID match.
Unlinked VMID + Conext ID match.
Linked VMID + Context ID match.
Unlinked CONTEXTIDR_EL2 match.
Linked CONTEXTIDR_EL2 match.
Unlinked Full Context ID match.
Linked Full Context ID match.
The field break down is:
BT[3:1]: Base type. If the breakpoint is not context-aware, these bits are res0. Otherwise, the possible values are:
Match address. DBGBVRn_EL1 is the address of an instruction.
Match context ID. DBGBVRn_EL1[31:0] is a context ID.
Match VMID. DBGBVRn_EL1[47:32] is a VMID.
Match VMID and CONTEXTIDR_EL1. DBGBVRn_EL1[31:0] is a context ID, and DBGBVRn_EL1[47:32] is a VMID.
- BT: Mismatch. res0.
- BT: Enable linking.
- LBN, [19:16]
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
- SSC, [15:14]
Security State Control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated.
This field must be interpreted with the Higher Mode Control (HMC), and Privileged Mode Control (PMC), fields to determine the mode and security states that can be tested.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for possible values of the HMC and PMC fields.
- HMC, 
Hyp Mode Control bit. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated.
This bit must be interpreted with the SSC and PMC fields to determine the mode and security states that can be tested.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for possible values of the SSC and PMC fields.
- RES0, [12:9]
- BAS, [8:5]
Byte Address Select. Defines which half-words a regular breakpoint matches, regardless of the instruction set and execution state. A debugger must program this field as follows:
Match the T32 instruction at DBGBVRn_EL1.
Match the T32 instruction at DBGBVRn+2_EL1.
Match the A64 or A32 instruction at DBGBVRn_EL1, or context match.
All other values are reserved.
The Armv8‑A architecture does not support direct execution of Java bytecodes. BAS and BAS ignore writes and on reads return the values of BAS and BAS respectively.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information on how the BAS field is interpreted by hardware.
- RES0, [4:3]
- PMC, [2:1]
Privileged Mode Control. Determines the Exception level or levels that a breakpoint debug event for breakpoint n is generated.
This field must be interpreted with the SSC and HMC fields to determine the mode and security states that can be tested.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for possible values of the SSC and HMC fields.
Bits[2:1] have no effect for accesses made in Hyp mode.
- E, 
Enable breakpoint. This bit enables the BRP:
A BRP never generates a breakpoint debug event when it is disabled.
The value of DBGBCRn_EL1.E is unknown on reset. A debugger must ensure that DBGBCRn_EL1.E has a defined value before it enables debug.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.