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TRCDEVAFF0, Device Affinity Register 0

The TRCDEVAFF0 provides an additional core identification mechanism for scheduling purposes in a cluster. TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.

Bit field descriptions

The TRCDEVAFF0 is a 32-bit register and is a copy of the MPIDR register. See MPIDR_EL1, Multiprocessor Affinity Register, EL1 for full bit field descriptions.