You copied the Doc URL to your clipboard.

TRCIDR0, ID Register 0

The TRCIDR0 returns the tracing capabilities of the ETM trace unit.

Bit field descriptions

The TRCIDR0 is a 32-bit register.

Figure D10-26 TRCIDR0 bit assignments

RES0, [31:30]

Indicates the meaning of the commit field in some packets:

1Commit mode 1.
TSSIZE, [28:24]

Global timestamp size field:

0b01000Implementation supports a maximum global timestamp of 64 bits.
RES0, [23:17]
QSUPP, [16:15]

Indicates Q element support:

0b00Q elements not supported.
QFILT, [14]

Indicates Q element filtering support:

0b0Q element filtering not supported.
CONDTYPE, [13:12]

Indicates how conditional results are traced:

0b00Conditional trace not supported.
NUMEVENT, [11:10]

Number of events supported in the trace, minus 1:

0b11Four events supported.

Return stack support:

1Return stack implemented.
RES0, [8]

Support for cycle counting in the instruction trace:

1Cycle counting in the instruction trace is implemented.

Support for conditional instruction tracing:

0Conditional instruction tracing is not supported.
TRCBB, [5]

Support for branch broadcast tracing:

1Branch broadcast tracing is implemented.
TRCDATA, [4:3]

Conditional tracing field:

0b00Tracing of data addresses and data values is not implemented.
INSTP0, [2:1]

P0 tracing support field:

0b00Tracing of load and store instructions as P0 elements is not supported.
RES1, [0]

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCIDR0 can be accessed through the external debug interface, offset 0x1E0.