TRCIDR1, ID Register 1
The TRCIDR1 returns the base architecture of the trace unit.
Bit field descriptions
The TRCIDR1 is a 32-bit register.
Figure D10-27 TRCIDR1 bit assignments
- DESIGNER, [31:24]
Indicates which company designed the trace unit:
- RES0, [23:16]
- RES1, [15:12]
- TRCARCHMAJ, [11:8]
Major trace unit architecture version number:
- TRCARCHMIN, [7:4]
Minor trace unit architecture version number:
- REVISION, [3:0]
Trace unit implementation revision number:
ETM revision for r1p1
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCIDR1 can be accessed through the external debug interface, offset