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TRCIDR8, ID Register 8

The TRCIDR8 returns the maximum speculation depth of the instruction trace stream.

Bit field descriptions

The TRCIDR8 is a 32-bit register.

Figure D10-32 TRCIDR8 bit assignments


MAXSPEC, [31:0]

The maximum number of P0 elements in the trace stream that can be speculative at any time.

0Maximum speculation depth of the instruction trace stream.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCIDR8 can be accessed through the external debug interface, offset 0x180.