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TRCIMSPEC0, Implementation Specific Register 0

The TRCIMSPEC0 shows the presence of any implementation specific features, and enables any features that are provided.

Bit field descriptions

The TRCIMSPEC0 is a 32-bit register.

Figure D10-38 TRCIMSPEC0 bit assignments

RES0, [31:4]
SUPPORT, [3:0]
0No implementation specific extensions are supported.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCIMSPEC0 can be accessed through the external debug interface, offset 0x1C0.