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TRCITATBCTR0, Trace Integration Test ATB Control Register 0

TRCITATBCTR0 controls signal outputs when TRCITCTRL.IME is set.

Bit field descriptions

The TRCITATBCTR0 is a 32-bit register.

Figure D10-39 TRCITATBCTR0 bit assignments


ATBYTESM[1:0], [9:8]
Drives the ATBYTESM outputs.
AFREADYM, [1]
Drives the AFREADYM output.
ATVALIDM, [0]
Drives the ATVALIDM output.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCITATBCTR0 register can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xEF8.