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TRCITCTRL, Trace Integration Mode Control register

TRCITCTRL controls whether the trace unit is in integration mode.

Bit field descriptions

The TRCITCTRL is a 32-bit RW management register that is reset to zero.

Figure D10-43 TRCITCTRL bit assignments


IME, [0]

Integration mode enable bit. The possible values are:

0b0The trace unit is not in integration mode.
0b1

The trace unit is in integration mode. This mode enables:

  • A debug agent to perform topology detection.
  • SoC test software to perform integration testing.
Usage constraints
  • Accessible only from the memory-mapped interface or from an external agent such as a debugger.
  • If the IME bit changes from one to zero then Arm recommends that the trace unit is reset. Otherwise the trace unit might generate incorrect or corrupt trace and the trace unit resources might behave unexpectedly.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCITCTRL register can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xF00.