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TRCLAR, Software Lock Access Register

The TRCLAR controls access to registers using the memory-mapped interface, when PADDRDBG31 is LOW.

Bit field descriptions

The TRCLAR is a 32-bit register.

Figure D10-46 TRCLAR bit assignments


RAZ/WI, [31:0]

Read-As-Zero, write ignore.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCLAR can be accessed through the external debug interface, offset 0xFB0.