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TRCLSR, Software Lock Status Register

The TRCLSR determines whether the software lock is implemented, and indicates the current status of the software lock.

Bit field descriptions

The TRCLSR is a 32-bit register.

Figure D10-47 TRCLSR bit assignments


RAZ/WI, [31:0]
Read-As-Zero, write ignore.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCLSR can be accessed through the external debug interface, offset 0xFB4.