TRCPDCR, Power Down Control Register
The TRCPDCR request to the system power controller to keep the ETM trace unit powered up.
Bit field descriptions
The TRCPDCR is a 32-bit register.
Figure D10-51 TRCPDCR bit assignments
- RES0, [31:4]
- PU, 
Powerup request, to request that power to the ETM trace unit and access to the trace registers is maintained:
Power not requested.
This bit is reset to 0 on a trace unit reset.
- RES0, [2:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCPDCR can be accessed through the external debug interface, offset