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TRCRSCTLRn, Resource Selection Control Registers 2-16

The TRCRSCTLRn controls the trace resources. There are eight resource pairs, the first pair is predefined as {0,1,pair=0} and having reserved select registers. This leaves seven pairs to be implemented as programmable selectors.

Bit field descriptions

The TRCRSCTLRn is a 32-bit register.

Figure D10-59 TRCRSCTLRn bit assignments

RES0, [31:22]

Inverts the result of a combined pair of resources.

This bit is implemented only on the lower register for a pair of resource selectors.

INV, [20]

Inverts the selected resources:

0Resource is not inverted.
1Resource is inverted.
RES0, [19]
GROUP, [18:16]

Selects a group of resources. See the Arm® ETM Architecture Specification, ETMv4 for more information.

RES0, [15:8]
SELECT, [7:0]

Selects one or more resources from the required group. One bit is provided for each resource from the group.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCRSCTLRn can be accessed through the external debug interface, offset 0x208-0x023C.