TRCSEQRSTEVR, Sequencer Reset Control Register
The TRCSEQRSTEVR resets the sequencer to state 0.
Bit field descriptions
The TRCSEQRSTEVR is a 32-bit register
Figure D10-61 TRCSEQRSTEVR bit assignments
- RES0, [31:8]
- RESETTYPE, 
Selects the resource type to move back to state 0:
Single selected resource.
Boolean combined resource pair.
- RES0, [6:4]
- RESETSEL, [3:0]
Selects the resource number, based on the value of RESETTYPE:
When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSEQRSTEVR can be accessed through the external debug interface, offset