TRCSSCCR0, Single-Shot Comparator Control Register 0
The TRCSSCCR0 controls the single-shot comparator.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
Figure D10-63 TRCSSCCR0 bit assignments
- RES0, [31:25]
- RST, 
Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:
Reset enabled. Multiple matches can occur.
- RES0, [23:20]
- ARC, [19:16]
Selects one or more address range comparators for single-shot control.
One bit is provided for each implemented address range comparator.
- RES0, [15:8]
- SAC, [7:0]
Selects one or more single address comparators for single-shot control.
One bit is provided for each implemented single address comparator.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSSCCR0 can be accessed through the external debug interface, offset