TRCSSCSR0, Single-Shot Comparator Status Register 0
The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction addresses.
Bit field descriptions
The TRCSSCSR0 is a 32-bit register
Figure D10-64 TRCSSCSR0 bit assignments
- STATUS, 
Single-shot status. This indicates whether any of the selected comparators have matched:
Match has not occurred.
Match has occurred at least once.
When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.
- RES0, [30:3]
- DV, 
Data value comparator support:
Single-shot data value comparisons not supported.
- DA, 
Data address comparator support:
Single-shot data address comparisons not supported.
- INST, 
Instruction address comparator support:
Single-shot instruction address comparisons supported.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.
The TRCSSCSR0 can be accessed through the external debug interface, offset