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TRCVIIECTLR, ViewInst Include-Exclude Control Register

The TRCVIIECTLR defines the address range comparators that control the ViewInst Include/Exclude control.

Bit field descriptions

The TRCVIIECTLR is a 32-bit register.

Figure D10-70 TRCVIIECTLR bit assignments


RES0, [31:20]
res0Reserved.
EXCLUDE, [19:16]
Defines the address range comparators for ViewInst exclude control. One bit is provided for each implemented Address Range Comparator.
RES0, [15:4]
res0Reserved.
INCLUDE, [3:0]

Defines the address range comparators for ViewInst include control.

Selecting no include comparators indicates that all instructions must be included. The exclude control indicates which ranges must be excluded.

One bit is provided for each implemented Address Range Comparator.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Embedded Trace Macrocell Architecture Specification ETMv4.

The TRCVIIECTLR can be accessed through the external debug interface, offset 0x084.