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Functional description

Table of Contents

Introduction
About the core
Features
Implementation options
Supported standards and specifications
Test features
Design tasks
Product revisions
Technical overview
Components
Instruction fetch
Instruction decode
Register rename
Instruction issue
Execution pipeline
L1 data memory system
L2 memory system
Interfaces
About system control
About the Generic Timer
Clocks, resets, and input synchronization
About clocks, resets, and input synchronization
Asynchronous interface
Power management
About power management
Voltage domains
Power domains
Architectural clock gating modes
Core Wait for Interrupt
Core Wait for Event
Power control
Core power modes
On
Off
Off (emulated)
Core dynamic retention
Debug recovery mode
Encoding for power modes
Power domain states for power modes
Power up and down sequences
Debug over powerdown
Memory Management Unit
About the MMU
Main functions
AArch64 behavior
TLB organization
Instruction L1 TLB
Data L1 TLB
L2 TLB
TLB match process
Translation table walks
AArch64 behavior
MMU memory accesses
Configuring MMU accesses
Descriptor hardware update
Specific behaviors on aborts and memory attributes
External aborts
Mis-programming contiguous hints
Memory attributes
Page Based Hardware Attributes
Level 1 memory system
About the L1 memory system
L1 instruction-side memory system
L1 data-side memory system
Cache behavior
Instruction cache disabled behavior
Instruction cache speculative memory accesses
Data cache disabled behavior
Data cache maintenance considerations
Data cache coherency
Write streaming mode
L1 instruction memory system
Program flow prediction
L1 data memory system
Memory system implementation
Internal exclusive monitor
Data prefetching
Direct access to internal memory
Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 BIM, L1 TLB instruction, and L0 macro-op cache data
Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data
Encoding for the L2 unified cache
Encoding for the L2 TLB
Level 2 memory system
About the L2 memory system
About the L2 cache
Support for memory types
Reliability, Availability, and Serviceability (RAS)
Cache ECC and parity
Cache protection behavior
Uncorrected errors and data poisoning
RAS error types
Error Synchronization Barrier
Error recording
Error injection
Generic Interrupt Controller CPU interface
About the Generic Interrupt Controller CPU interface
Bypassing the CPU interface
Advanced SIMD and floating-point support
About the Advanced SIMD and floating-point support
Accessing the feature identification registers
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