About clocks, resets, and input synchronization
The Cortex®‑A77 core supports hierarchical clock gating.
The Cortex‑A77 core contains several interfaces that connect to other components in the system. These interfaces can be in the same clock domain or in other clock domains.
For information about clocks, resets, and input synchronization, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.