About the Generic Interrupt Controller CPU interface
The Cortex®‑A77 core implements the GIC CPU interface as described in the Arm® Generic Interrupt Controller Architecture Specification.
This interfaces with an external GICv3 or GICv4 distributor component within the cluster system and is a resource for supporting and managing interrupts. The GIC CPU interface hosts registers to mask, identify and control states of interrupts forwarded to that core. Each core in the cluster system has a GIC CPU interface component and connects to a common external distributor component.
NoteThis chapter describes only features that are specific to the Cortex‑A77 core implementation. Additional information specific to the cluster can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual.
The GICv4 architecture supports:
- Two security states.
- Interrupt virtualization.
- Software-generated Interrupts (SGIs).
- Message Based Interrupts.
- System register access for the CPU interface.
- Interrupt masking and prioritization.
- Cluster environments, including systems that contain more than eight cores.
- Wake-up events in power management environments.
The GIC includes interrupt grouping functionality that supports:
- Configuring each interrupt to belong to an interrupt group.
- Signaling Group 1 interrupts to the target core using either the IRQ or the FIQ exception request. Group 1 interrupts can be Secure or Non-secure.
- Signaling Group 0 interrupts to the target core using the FIQ exception request only.
- A unified scheme for handling the priority of Group 0 and Group 1 interrupts.
This chapter describes only features that are specific to the Cortex‑A77 core implementation.