About the core
The Cortex®‑A77 core is a high-performance and low-power Arm product that implements the Arm®v8‑A architecture.
The Cortex‑A77 core supports:
- The Armv8.2-A extension.
- The Reliability, Availability, and Serviceability (RAS) extension.
- The Load acquire (
LDAPR) instructions introduced in the Armv8.3-A extension
- The Dot Product support instructions introduced in the Armv8.4-A extension.
- The PSTATE Speculative Store Bypass Safe (SSBS) bit introduced in the Armv8.5‑A extension.
The Cortex‑A77 core has a Level 1 (L1) memory system and a private, integrated Level 2 (L2) cache. It also includes a superscalar, variable-length, out-of-order pipeline.
The Cortex‑A77 core is implemented inside the DynamIQ Shared Unit (DSU) cluster. For more information, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.
The following figure shows an example of a configuration with four Cortex‑A77 cores.
Figure A1-1 Example Cortex‑A77 configuration