L1 instruction-side memory system
The L1 instruction memory system has the following key features:
- Virtually Indexed, Physically Tagged (VIPT) 4-way set-associative L1 instruction cache, which behaves as a Physically Indexed, Physically Tagged (PIPT) cache.
- Fixed cache line length of 64 bytes.
- Pseudo-LRU cache replacement policy.
- 256-bit read interface from the L2 memory system.
The Cortex®‑A77 core also has a Virtually Indexed, Virtually Tagged (VIVT) 4-way set-associative, Macro-OP (MOP) cache, which behaves as a Physically Indexed, Physically Tagged (PIPT) cache.