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Cache behavior

The implementation specific features of the instruction and data caches include:

  • At reset the instruction and data caches are disabled and both caches are automatically invalidated.


Caches in the core are invalidated automatically at reset deassertion unless the core power mode is initialized to Debug recovery. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information.
  • You can enable or disable each cache independently.
  • Cache lockdown is not supported.
  • On a cache miss, data for the cache linefill is requested in critical word-first order.
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