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Data cache disabled behavior

If the data cache is disabled, load and store instructions do not access any of the L1 data, L2 cache, and, if present, the DynamIQ Shared Unit (DSU) L3 cache arrays.

When the data cache is disabled, instructions and operations are affected as follows:

  • An instruction fetch does not allocate a new line in the L2 or L3 caches.
  • All load and store instructions to cacheable memory are treated as if they were Non-cacheable and are incoherent with the caches in both this core and other cores in the cluster. Software must take this into account.
  • Data cache maintenance operations are an exception and will execute normally.


The L2 and L1 data caches cannot be disabled independently.
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