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Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 BIM, L1 TLB instruction, and L0 macro-op cache data

The following tables show the encoding required to select a given cache line.

Table A6-2 L1 instruction cache tag location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x00
[23:20] Reserved
[19:18] Way
[17:14] Reserved
[13:6] Index [13:6]
[5:0] Reserved

Table A6-3 L1 instruction cache data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x01
[23:20] Reserved
[19:18] Way
[17:14] Reserved
[13:3] Index [13:3]
[2:0] Reserved

Table A6-4 L1 BTB data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x02
[23:16] Reserved
[15:4] Index [15:4]
[3:0] Reserved

Table A6-5 L1 GHB data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x03
[23:15] Reserved
[14:5] Index [14:5]
[4:0] Reserved

Table A6-6 BIM data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x05
[23:14] Reserved
[13:4] Index [13:4]
[3:0] Reserved

Table A6-7 L1 instruction TLB data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x04
[23:8] Reserved
[7:0] TLB Entry (->47)

Table A6-8 L0 Macro-op cache data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x06
[23:10] Reserved
[9:0] Index [9:0]

instruction tag RAM

The following tables show the data that is returned from accessing the L1 instruction tag RAM.

Table A6-9 L1 instruction cache tag format for instruction register 0

Bit field Description

[31]

Non-secure identifier for the physical address

[30:3]

Physical address [39:12]

[2:1]

Instruction state [1:0]

00Invalid
01T32
10A32
11A64
[0]

Parity

Table A6-10 L1 instruction cache tag format for instruction register 1

Bit field Description
[63:0] 0

Table A6-11 L1 instruction cache tag format for instruction register 2

Bit field Description
[63:0] 0

instruction data RAM

The following tables show the data that is returned from accessing the L1 instruction data RAM.

Table A6-12 L1 instruction cache data format for instruction register 0

Bit field Description
[63:0] Data [63:0]

Table A6-13 L1 instruction cache data format for instruction register 1

Bit field Description
[63:9] 0
[8] Parity
[7:0] Data [71:64]

Table A6-14 L1 instruction cache data format for instruction register 2

Bit field Description
[63:0] 0

BTB RAM

The following tables show the data that is returned from accessing the L1 BTB RAM.

Table A6-15 L1 BTB cache format for instruction register 0

Bit field Description
[63:0] Data [63:0]

Table A6-16 L1 BTB cache format for instruction register 1

Bit field Description

[63:18]

0

[17:0]

Data [81:64]

Table A6-17 L1 BTB cache format for instruction register 2

Bit field Description
[63:0] 0

L1 GHB RAM

The following tables show the data that is returned from accessing the L1 GHB RAM.

Table A6-18 L1 GHB cache format for instruction register 0

Bit field Description
[63:0] Data [63:0]

Table A6-19 L1 GHB cache format for instruction register 1

Bit field Description
[63:32] 0
[31:0] Data [95:64]

Table A6-20 L1 GHB cache format for instruction register 2

Bit field Description
[63:0] 0

BIM RAM

The following tables show the data that is returned from accessing the L1 BIM RAM.

Table A6-21 L1 BIM cache format for instruction register 0

Bit field Description
[63:16] 0
[15:0] Data [15:0]

Table A6-22 L1 BIM cache format for instruction register 1

Bit field Description
[63:0] 0

Table A6-23 L1 BIM cache format for instruction register 2

Bit field Description
[63:0] 0

instruction TLB RAM

The following tables show the data that is returned from accessing the L1 instruction TLB RAM.

Table A6-24 L1 instruction TLB cache format for instruction register 0

Bit field Description
[63:59]

Virtual address [16:12]

[58:57] PBHA [1:0]
[56] TLB attribute
[55:53]

Memory attributes:

000Device nGnRnE
001Device nGnRE
010Device nGRE
011Device GRE
100Non-cacheable
101Write-Back No-Allocate
110Write-Back Transient
111Write-Back Read-Allocate and Write-Allocate
[52:50]

Page size:

0004KB
00116KB
01064KB
011256KB
1002MB
10132MB
11xReserved
[49:46] TLB attribute
[45] Outer-shared
[44] Inner-shared
[43:39] TLB attribute
[38:23] ASID
[22:7] VMID
[6:5]

Translation regime:

00Secure EL1/EL0
01Secure EL3
10Non-secure EL1/EL0
11Non-secure EL2
[4:1] TLB attribute
[0] Valid

Table A6-25 L1 instruction TLB cache format for instruction register 1

Bit field Description
[60]

Non-secure

[59:32] Physical address [39:12]
[31:0] Virtual address [48:17]

macro-op RAM

The following tables show the data that is returned from accessing the L0 macro-op RAM.

Table A6-26 L0 Macro-op cache format for instruction register 0

Bit field Description
[63:0] Macro-op data [63:0]

Table A6-27 L0 Macro-op cache format for instruction register 1

Bit field Description

[63:34]

0

[33:0]

Macro-op data [97:64]

Table A6-28 L0 Macro-op cache format for instruction register 2

Bit field Description
[63:0] 0
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