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Encoding for the L2 TLB

The following section describes the encoding for L2 TLB direct accesses.

The following table shows the encoding that is required to select a given TLB entry.

Table A6-64 L2 TLB encoding

Bit fields of Rd Description
[31:24] RAMID = 0x18
[23:21] Reserved
[20:18] Way
0b000way0
0b001way1
0b010way2
0b011way3
0b100way4
[17:8] Reserved
[7:0] Index

TLB

The following tables show the data that is returned from accessing the L2 TLB.

Table A6-65 L2 TLB format for instruction register 0

Bit field Description
[63] Outer-shared
[62] Inner-shared
[61] Reserved
[60:58]

Memory attributes:

0b000Device nGnRnE
0b001Device nGnRE
0b010Device nGRE
0b011Device GRE
0b100Non-cacheable
0b101Write-Back No-Allocate
0b110Write-Back Transient
0b111Write-Back Read-Allocate and Write-Allocate
[57:54]

Reserved

[53:20]

Physical address

When bit[6] is 0:

  • [53:26] = PA[39:12]
  • [25:20] = Don't care

When bit[6] is 1:

  • [53:28] = PA[39:14]
  • [27:26] = PA[13:12] for page 3 (highest memory address)
  • [25:24] = PA[13:12]for page 2
  • [23:22] = PA[13:12]for page 1
  • [21:20] = PA[13:12]for page 0 (lowest memory address)
[19:17]

Page size:

0b0004KB
0b00116KB
0b01064KB
0b011256KB
0b1002MB
0b10132MB
0b110512MB
0b1111GB
[16:7] Reserved
[6] Indicates that the entry is coalesced and holds translations for up to four contiguous pages
[5:2] This bit field contains the valid bits for four contiguous pages. If the entry is non-coalesced, then 0b0001 indicates a valid entry.
[1:0] Reserved

Table A6-66 L2 TLB format for instruction register 1

Bit field Description
[63:62]

VMID [1:0]

[61:46] ASID [15:0]
[45:44] PBHA [1:0]
[43] Walk cache entry
[42]  
[41:13] Virtual address [48:20]
[12] Non-secure
[11:1] Reserved
[0] Non-global

Table A6-67 L2 TLB format for instruction register 2

Bit field Description
[63:16]

Reserved

[15:14]

Translation regime:

0b00Secure EL1
0b01EL3
0b10Non-secure EL1
0b11EL2
[13:0] VMID [15:2]
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