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Encoding for the L2 unified cache

The following tables show the encoding required to select a given cache line.

Table A6-46 L2 tag location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x10
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved

Table A6-47 L2 data location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x11
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:4] Index[15:4]
[3:0] Reserved

Table A6-48 L2 victim location encoding

Bit fields of Rd Description
[31:24] RAMID = 0x12
[23:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved

tag RAM when L2 is configured with a 128KB cache size

The following tables show the data that is returned from accessing the L2 tag RAM when L2 is configured with a 128KB cache size.

Table A6-49 L2 tag format with a 128KB L2 cache size for data register 0

Bit field Description

[63:47]

0
[46:40] ECC [6:0] if configured with ECC for a 128KB L2 cache size, otherwise 0
[39:38] PBHA [1:0]

[37:12]

Physical address [39:14]

[11] Non-secure identifier for the physical address
[10:9] Virtual index [13:12]
[8:6] Reserved
[5] Shareable
[4] Outer allocation hint
[3] L1 data cache valid
[2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid

Table A6-50 L2 tag format with a 128KB L2 cache size for data register 1

Bit field Description
[63:0] 0

Table A6-51 L2 tag format with a 128KB L2 cache size for data register 2

Bit field Description
[63:0] 0

tag RAM when L2 is configured with a 256KB cache size

The following tables show the data that is returned from accessing the L2 tag RAM when L2 is configured with a 256KB cache size.

Table A6-52 L2 tag format with a 256KB L2 cache size for data register 0

Bit field Description

[63:46]

0
[45:39] ECC [6:0] if configured with ECC for a 256KB L2 cache size, otherwise 0
[38:37] PBHA [1:0]

[36:12]

Physical address [39:15]

[11] Non-secure identifier for the physical address
[10:9] Virtual index [13:12]
[8:6] Reserved
[5] Shareable
[4] Outer allocation hint
[3] L1 data cache valid
[2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid

Table A6-53 L2 tag format with a 256KB L2 cache size for data register 1

Bit field Description
[63:0] 0

Table A6-54 L2 tag format with a 256KB L2 cache size for data register 2

Bit field Description
[63:0] 0

tag RAM when L2 is configured with a 512KB cache size

The following tables show the data that is returned from accessing the L2 tag RAM when L2 is configured with a 512KB cache size.

Table A6-55 L2 tag format with a 512KB L2 cache size for data register 0

Bit field Description

[63:45]

0
[44:38] ECC [6:0] if configured with ECC for a 512KB L2 cache size, otherwise 0
[37:36]

PBHA [1:0]. PBHA is always present and has no dependency on ECC or non-ECC.

[35:12]

Physical address [39:16]

[11] Non-secure identifier for the physical address
[10:9] Virtual index [13:12]
[8:6] Reserved
[5] Shareable
[4] Outer allocation hint
[3] L1 data cache valid
[2:0]

L2 State

101Modified
001Exclusive
x11Shared
xx0Invalid

Table A6-56 L2 tag format with a 512KB L2 cache size for data register 1

Bit field Description
[63:0] 0

Table A6-57 L2 tag format with a 512KB L2 cache size for data register 2

Bit field Description
[63:0] 0

data RAM

The following tables show the data that is returned from accessing the L2 data RAM.

Table A6-58 L2 data format for data register 0

Bit field Description
[63:0] Data [63:0]

Table A6-59 L2 data format for data register 1

Bit field Description
[63:0] Data [127:64]

Table A6-60 L2 data format for data register 2

Bit field Description
[63:16] 0
[15:8] ECC for Data [127:64] if configured with ECC
[7:0] ECC for Data [63:0] if configured with ECC

victim RAM

The following tables show the data that is returned from accessing the L2 victim RAM.

Table A6-61 L2 victim format for data register 0

Bit field Description
[63:16] 0
[15:0] Replacement [15:0]

Table A6-62 L2 victim format for data register 1

Bit field Description
[63:0] 0

Table A6-63 L2 victim format for data register 2

Bit field Description
[63:0] 0
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