You copied the Doc URL to your clipboard.

About the L2 cache

The integrated L2 cache is the Point of Unification for the Cortex®‑A77 core. It handles both instruction and data requests from the instruction side and data side of each core respectively.

When fetched from the system, instructions are allocated to the L2 cache and can be invalidated during maintenance operations.


Caches in the core are invalidated automatically at reset deassertion unless the core power mode is initialized to Debug recovery. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information.
Was this page helpful? Yes No