The memory region attributes specified in the TLB entry, or in the descriptor in case of translation table walk, determine if the access is:
- Normal Memory or Device type.
- One of the four different device memory types that are defined for Armv8:
Device-nGnRnE Device non-Gathering, non-Reordering, No Early Write Acknowledgement. Device-nGnRE Device non-Gathering, non-Reordering, Early Write Acknowledgement. Device-nGRE Device non-Gathering, Reordering, Early Write Acknowledgement. Device-GRE Device Gathering, Reordering, Early Write Acknowledgment.
In the Cortex®‑A77 core, a page is cacheable only if the Inner and Outer memory attributes are Write Back. In all other cases, all pages are downgraded to Non-cacheable Normal memory.
When the Memory Management Unit (MMU) is disabled at stage 1 and stage 2, and SCTLR.I is set to 1, instruction prefetches are cached in the instruction cache but not in the unified cache. In all other cases, normal behavior on memory attribute applies.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information on translation table formats.