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The L2 TLB structure is shared by instruction and data. It handles misses from the instruction and data L1 TLBs.

The following table describes the L2 TLB characteristics.

Table A5-3 L2 TLB characteristics

Characteristic Note
5-way, set associative, 1280-entry cache


  • Virtual Address (VA) to Physical Address (PA) mappings for 4KB, 16KB, 64KB, 2MB, 32MB, 512MB, and 1GB block sizes.
  • Intermediate physical address (IPA) to PA mappings for 2MB and 1GB (in a 4KB translation granule), 32MB (in a 16K translation granule), and 512MB (in a 64K granule) block sizes. Only Non-secure EL1 and EL0 stage 2 translations are cached.
  • Intermediate PAs obtained during a translation table walk.

Access to the L2 TLB usually takes three cycles. If a different page or block size mapping is used, then this access can take longer.

The L2 TLB supports four translation table walks in parallel (four TLB misses), and can service two TLB lookups while the translation table walks are in progress. If there are six successive misses, the L2 TLB will stall.


Caches in the core are invalidated automatically at reset deassertion unless the core power mode is initialized to Debug recovery. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for more information.
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