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Translation table walks

When an access is requested at an address, the Memory Management Unit (MMU) searches for the requested Virtual Address (VA) in the Translation Lookaside Buffers (TLBs). If it is not present, then it is a miss and the translation proceeds by looking up the translation table during a translation table walk.

When the Cortex®‑A77 core generates a memory access, the following process occurs:

  1. The MMU performs a lookup for the requested Virtual Address (VA), current Address Space Identifier (ASID), current Virtual Machine Identifier (VMID), and current translation regime in the relevant instruction or data L1 TLB.
  2. If there is a miss in the relevant L1 TLB, the MMU performs a lookup in the L2 TLB for the requested VA, current ASID, current VMID, and translation regime.
  3. If there is a miss in the L2 TLB, the MMU performs a hardware translation table walk.

In the case of an L2 TLB miss, the hardware does a translation table walk as long as the MMU is enabled, and the translation using the base register has not been disabled.

If the translation table walk is disabled for a particular base register, the core returns a translation fault. If the TLB finds a matching entry, it uses the information in the entry as follows.

The access permission bits determine whether the access is permitted. If the matching entry does not pass the permission checks, the MMU signals a Permission fault. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for details of Permission faults.

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