Core Wait for Interrupt
WFI uses a locking mechanism, based on events, to put the core in a low-power state by disabling most of the clocks in the core, while keeping the core powered up.
When the core executes the
WFI instruction, the core waits for all instructions in the core, including explicit memory accesses, to retire before it enters a low-power state. The
WFI instruction also ensures that store instructions have updated the cache or have been issued to the L3 memory system.
While the core is in WFI low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFI low-power state when any of the following events are detected:
- An L3 snoop request that must be serviced by the core data caches.
- A cache or TLB maintenance operation that must be serviced by the core L1 instruction cache, data cache, TLB, or L2 cache.
- An APB access to the debug or trace registers residing in the core power domain.
- A GIC CPU access through the AXI4 stream channel.
Exit from WFI low-power state occurs when one of the following occurs:
- The core detects one of the WFI wake-up events.
- The core detects a reset.
For more information, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.