Core dynamic retention
The Core dynamic retention mode can be enabled and disabled separately for WFI and WFE by software running on the core. Separate timeout values can be programmed for entry into this mode from WFI and WFE mode:
- Use the CPUPWRCTLR.WFI_RET_CTRL register bits to program timeout values for entry into Core dynamic retention mode from WFI mode.
- Use the CPUPWRCTLR.WFE_RET_CTRL register bits to program timeout values for entry into Core dynamic retention mode from WFE mode.
The clock to the core is automatically gated outside of the domain when the core is in Core dynamic retention mode and is running synchronously to the cluster. However, if the core is running asynchronously to the cluster, the system integrator must gate the clock externally during Core dynamic retention mode. For more information, see the Arm® DynamIQ™ Shared Unit Configuration and Sign-off Guide.
The outputs of the domain must be isolated to prevent buffers without power from propagating unknown values to any operational parts of the system.
When the core is in Core dynamic retention mode there is support for snoop, GIC, and debug access, so the core appears as if it were in WFI or WFE mode. When an incoming access occurs, it stalls, and the On PACTIVE bit is set HIGH. The incoming access proceeds when the domain is returned to the On mode using P-Channel.
When the incoming access completes, and if the core has not exited WFI or WFE mode, then the On PACTIVE bit is set LOW after the programmed retention timeout. The power controller can then request to reenter the Core dynamic retention mode.