Debug recovery mode
The Debug recovery mode assists with debugging external watchdog-triggered reset events.
It allows contents of the core L1 data cache that were present before the reset to be observable after the reset. The contents of the L1 cache are retained and are not altered on the transition back to the On mode.
By default, the core invalidates its caches when power-on reset (nCPUPORESET) is deasserted. If the P-Channel is initialized to the Debug recovery mode, and the core is cycled through power-on reset along with the system power-on reset, then the cache invalidation is disabled. Initializing the P-Channel to the Debug recovery mode ensures that the cache contents are preserved when the core is transitioned to the On mode.
Debug recovery mode also supports preserving the RAS state, in addition to the cache contents. In this case, a transition to the Debug recovery mode is made from any of the current states. Once in Debug recovery mode, the core is cycled through a Warm reset with the system Warm reset. The RAS and cache state are preserved when the core is transitioned to the On mode.
This mode is strictly for debug purposes. It must not be used for functional purposes, because the correct operation of the L1 cache is not guaranteed when entering this mode.