You copied the Doc URL to your clipboard.

Emulated off

In this mode, all core domain logic and RAMs are kept on. However, core Warm reset can be asserted externally to emulate a power off scenario while keeping core debug state and allowing debug access.

All debug registers must retain their mode and be accessible from the external debug interface. All other functional interfaces behave as if the core was in Off mode.

Was this page helpful? Yes No