The Cortex®‑A77 core supports a full shutdown mode where power can be removed completely and no state is retained.
The shutdown can be for either the whole cluster or just for an individual core, which allows other cores in the cluster to continue operating.
In this mode, all core logic and RAMs are off. The domain is inoperable and all core state is lost. The L1 and L2 caches are disabled, flushed and the core is removed from coherency automatically on transition to Off mode.
A Cold reset can reset the core in this mode.
The core P-Channel can be initialized into this mode.
An attempted debug access when the core domain is off returns an error response on the internal debug interface indicating the core is not available.