All power mode transitions are performed at the request of the power controller, using a P-Channel interface to communicate with the Cortex®‑A77 core.
There is one P-Channel per core, plus one P-Channel for the cluster. The Cortex‑A77 core provides the current requirements on the PACTIVE signals, so that the power controller can make decisions and request any change with PREQ and PSTATE. The Cortex‑A77 core then performs any actions necessary to reach the requested power mode, such as gating clocks, flushing caches, or disabling coherency, before accepting the request.
If the request is not valid, either because of an incorrect transition or because the status has changed so that state is no longer appropriate, then the request is denied. The power mode of each core can be independent of other cores in the cluster, however the cluster power mode is linked to the mode of the cores.