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Power domains

The Cortex®‑A77 core contains a core power domain (PDCPU) and a core top-level SYS power domain (PDSYS) where all the Cortex‑A77 core I/O signals go through.

PDCPU power domain

The PDCPU power domain contains:

  • All deimos_cpu logic.
  • The part of the asynchronous bridge that belongs to the VCPU domain.
  • The Advanced SIMD and floating-point unit.
  • The L1 and L2 RAMs

PDSYS power domain

The PDSYS power domain contains the part of the core asynchronous bridge that belongs to the DSU power domain.


There are additional system power domains in the DSU. See the Arm® DynamIQ™ Shared Unit Technical Reference Manual for information.

The following figure shows an example of how the voltage and power domains are organized.

Figure A4-2 Cortex‑A77 core power domain diagram at the deimos_core level

The following table describes the power domains that the Cortex‑A77 core supports.

Table A4-1 Power domain description

Power domain Hierarchy Description
PDCPU<n> u_vcpu

The domain includes the Advanced SIMD and floating-point block, the L1 and L2 TLBs, L1 and L2 cache RAMs, and Debug registers that are associated with the Cortex‑A77 core.

<n> is the core number in the range 0-3. The number represents core 0, core 1, core 2, and core 3. If a core is not present, then the corresponding power domain is not present.

PDSYS Top-level hierarchy and everything outside u_vcpu

The domain is the interface between Cortex‑A77 and the DSU. It contains the cluster clock domain logic of the CPU bridge. The CPU Bridge contains all asynchronous bridges for crossing clock domains, and is split with one half of each bridge in the core clock domain and the other half in the relevant cluster domain. All core I/O signals go through the CPU bridge and the SYS power domain.

The domain is shared between the DSU and Cortex‑A77 hierarchies, and contains the following:

  • Anything outside of the core power domain (u_vcpu hierarchy).
  • u_cb_sys.

Clamping cells between power domains are inferred through power intent files rather than instantiated in the RTL.

The following figure shows the power domains in the DSU cluster, where everything in the same color is part of the same power domain. The number of Cortex‑A77 cores can vary, and the number of domains increases based on the number of Cortex‑A77 cores present. This example only shows four Cortex‑A77 cores and the power domains that are associated with them. Other power domains are required for a DSU cluster and are not shown in this example.

Figure A4-3 Cortex‑A77 power domains

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