The instruction fetch unit fetches instructions from the L1 instruction cache and delivers the instruction stream to the instruction decode unit.
The instruction fetch unit includes:
- A 64KB, 4-way, set associative L1 instruction cache with 64-byte cache lines and optional parity protection.
- A fully associative L1 instruction TLB with native support for 4KB, 16KB, 64KB, 2MB, and 32MB page sizes.
- A 1.5K entry, 4-way skewed associative L0 Macro-OP (MOP) cache with optional parity, which contains decoded and optimized instructions for higher performance.
- A dynamic branch predictor.