L2 memory system
The L2 memory system services L1 instruction and data cache misses in the Cortex®‑A77 core.
The L2 memory system includes:
- An 8-way set associative L2 cache with data ECC protection per 64 bits. The L2 cache is configurable with sizes of 128KB, 256KB, or 512KB.
- An interface with the DynamIQ Shared Unit (DSU) configurable at implementation time for synchronous or asynchronous operation.