MPIDR_EL1, Multiprocessor Affinity Register, EL1
The MPIDR_EL1 provides an additional core identification mechanism for scheduling purposes in a cluster.
Bit field descriptions
MPIDR_EL1 is a 64-bit register, and is part of the Other system control registers functional group.
This register is Read Only.
Figure B2-75 MPIDR_EL1 bit assignments
- RES0, [63:40]
- Aff3, [39:32]
Affinity level 3. Highest level affinity field.
- Indicates the value read in the CLUSTERIDAFF3 configuration signal.
- RES1, 
- U, 
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Core is part of a multiprocessor system. This is the value for implementations with more than one core, and for implementations with an ACE or CHI master interface.
- RES0, [29:25]
- MT, 
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multithreading type approach. This value is:
Performance of PEs at the lowest affinity level is very interdependent.
Affinity0 represents threads. Cortex®‑A77 is not multithreaded, but may be in a system with other cores that are multithreaded.
- Aff2, [23:16]
Affinity level 2. Second highest level affinity field.
- Indicates the value read in the CLUSTERIDAFF2 configuration signal.
- Aff1, [15:11]
- Part of Affinity level 1. Third highest level affinity field.
- Aff1, [10:8]
Part of Affinity level 1. Third highest level affinity field.
CPUID Identification number for each CPU in the cluster:
MP1: CPUID: 0. to
MP8: CPUID: 7.
- Aff0, [7:0]
- Affinity level 0. The level identifies individual threads within a multithreaded core. The Cortex‑A77 core is single-threaded, so this field has the value
MPIDR_EL1[31:0] is mapped to external register EDDEVAFF0.
MPIDR_EL1[63:32] is mapped to external register EDDEVAFF1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.