Effects of resets on debug registers
The core has the following reset signals that affect the debug registers:
- This signal initializes the core logic, including the debug, ETM trace unit, breakpoint, watchpoint logic, and performance monitors logic. This maps to a Cold reset that covers reset of the core logic and the integrated debug functionality.
- This signal resets some of the debug and performance monitor logic. This maps to a Warm reset that covers reset of the core logic.