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PMU events

The following table shows the events that are generated and the numbers that the PMU uses to reference the events. The table also shows the bit position of each event on the event bus. Event reference numbers that are not listed are reserved.

Table C2-1 PMU Events

Event number PMU event bus (to trace) Event mnemonic Event description
0x0 [00] SW_INCR Software increment. Instruction architecturally executed (condition code check pass).
0x1 [01] L1I_CACHE_REFILL

L1 instruction cache refill. This event counts any instruction fetch which misses in the cache.

The following instructions are not counted:

  • Cache maintenance instructions.
  • Non-cacheable accesses.
0x2 [02] L1I_TLB_REFILL

L1 instruction TLB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.

The following instructions are not counted:

  • TLB maintenance instructions.

This event counts regardless of whether the MMU is enabled.

0x3 [170] L1D_CACHE_REFILL

L1 data cache refill. This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Stores of an entire cache line, even if they make a coherency request outside the L1.
  • Partial cache line writes which do not allocate into the L1 cache.
  • Non-cacheable accesses.

This event counts the sum of L1D_CACHE_REFILL_RD and L1D_CACHE_REFILL_WR.

0x4 [05:03] L1D_CACHE

L1 data cache access. This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Non-cacheable accesses.

This event counts the sum of L1D_CACHE_RD and L1D_CACHE_WR.

0x5 [07:06] L1D_TLB_REFILL

L1 data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault. The following instructions are not counted:

  • TLB maintenance instructions.

This event counts regardless of whether the MMU is enabled.

0x8 [12:08] INST_RETIRED

Instruction architecturally executed. This event counts all retired instructions, including those that fail their condition check.

0x9 [13] EXC_TAKEN Exception taken.
0x0A [14] EXC_RETURN Instruction architecturally executed, condition code check pass, exception return.
0x0B [160] CID_WRITE_RETIRED

Instruction architecturally executed, condition code check pass, write to CONTEXTIDR. This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.

The following instructions are not counted:

  • Writes to CONTEXTIDR_EL12 and CONTEXTIDR_EL2.
0x10 [15] BR_MIS_PRED

Mispredicted or not predicted branch speculatively executed. This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken.

0x11 [177] CPU_CYCLES Cycle
0x12 [17:16] BR_PRED

Predictable branch speculatively executed. This event counts all predictable branches.

0x13 [20:18] MEM_ACCESS

Data memory access. This event counts memory accesses due to load or store instructions.

The following instructions are not counted:

  • Instruction fetches.
  • Cache maintenance instructions.
  • Translation table walks or prefetches.
This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.
0x14 [21] L1I_CACHE

Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.

The following instructions are not counted:
  • Cache maintenance instructions.
  • Non-cacheable accesses.
0x15 [22] L1D_CACHE_WB

L1 data cache Write-Back. This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.

The following instructions are not counted:

  • Invalidations which do not result in data being transferred out of the L1.
  • Full-line writes which write to L2 without writing L1, such as write streaming mode.
0x16 [25:23] L2D_CACHE

L2 data cache access. This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.

0x17 [28:26] L2D_CACHE_REFILL

L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes and prefetches that target this level of cache, should not be counted.

0x18 [31:29] L2D_CACHE_WB

L2 data cache write-back. This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted.

0x19 [33:32] BUS_ACCESS

Bus access. This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.

0x1A [34] MEMORY_ERROR

Local memory error. This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs.

0x1B [38:35] INST_SPEC Operation speculatively executed
0x1C [179] TTBR_WRITE_RETIRED

Instruction architecturally executed, condition code check pass, write to TTBR.This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.

The following instructions are not counted:

  • Accesses to TTBR0_EL12/TTBR1_EL12 or TTBR0_EL2/TTBR1_EL2.
0x1D [39] BUS_CYCLES

Bus cycles. This event duplicates CPU_CYCLES.

0x1E [40] CHAIN

For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered counter. For even-numbered counters, there is no increment.

0x20 [42:41] L2D_CACHE_ALLOCATE

L2 data cache allocation without refill. This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.

0x21 [44:43] BR_RETIRED

Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.

0x22 [46:45] BR_MIS_PRED_RETIRED

Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.

0x23 [172] STALL_FRONTEND

No operation issued because of the frontend. The counter counts on any cycle when there are no fetched instructions available to dispatch.

0x24 [173] STALL_BACKEND

No operation issued because of the backend. The counter counts on any cycle fetched instructions are not dispatched due to resource constraints.

0x25 [49:47] L1D_TLB

Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.

0x26 [171] L1I_TLB

Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled.

0x29 [159] L3D_CACHE_ALLOCATE Attributable L3 data or unified cache allocation without refill. This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2.
0x2A [162:161] L3D_CACHE_REFILL

Attributable Level 3 unified cache refill.

This event counts for any cacheable read transaction returning data from the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions.

Prefetches and stashes that target the L3 cache are not counted.

0x2B [163] L3D_CACHE

Attributable Level 3 unified cache access.

This event counts for any cacheable read transaction returning data from the SCU, or for any cacheable write to the SCU.

0x2D [50] L2D_TLB_REFILL

Attributable L2 data or unified TLB refill. This event counts on any refill of the L2 TLB, caused by either an instruction or data access. This event does not count if the MMU is disabled.

0x2F [52:51] L2D_TLB

Attributable L2 data or unified TLB access. This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.

0x31 [164] REMOTE_ACCESS Access to another socket in a multi-socket system.
0x34 [53] DTLB_WALK

Access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count.

0x35 [54] ITLB_WALK

Access to instruction TLB that caused a page table walk. This event counts on any instruction access which causes L2D_TLB_REFILL to count.

0x36 [166:165] LL_CACHE_RD

Last level cache access, read.

  • If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'interconnect cache'.
  • If CPUECTLR.EXTLLC is not set: This event is a duplicate of the L*D_CACHE_RD event corresponding to the last level of cache implemented - L3D_CACHE_RD if both per-core L2 and cluster L3 are implemented, L2D_CACHE_RD if only one is implemented, or L1D_CACHE_RD if neither is implemented.
0x37 [168:167] LL_CACHE_MISS_RD

Last level cache miss, read.

  • If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'DRAM', 'remote' or 'inter-cluster peer'.
  • If CPUECTLR.EXTLLC is not set: This event is a duplicate of the L*D_CACHE_REFILL_RD event corresponding to the last level of cache implemented - L3D_CACHE_REFILL_RD if both per-core L2 and cluster L3 are implemented, L2D_CACHE_REFILL_RD if only one is implemented, or L1D_CACHE_REFILL_RD if neither is implemented.

0x40 [56:55] L1D_CACHE_RD

L1 data cache access, read. This event counts any load operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL_RD event causes this event to count.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Non-cacheable accesses.
0x41 [58:57] L1D_CACHE_WR

L1 data cache access, write. This event counts any store operation which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL_WR event causes this event to count.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Non-cacheable accesses.
0x42 [59] L1D_CACHE_REFILL_RD

L1 data cache refill, read. This event counts any load operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Non-cacheable accesses.
0x43 [60] L1D_CACHE_REFILL_WR

L1 data cache refill, write. This event counts any store operation which causes data to be read from outside the L1, including accesses which do not allocate into L1.

The following instructions are not counted:

  • Cache maintenance instructions and prefetches.
  • Stores of an entire cache line, even if they make a coherency request outside the L1.

  • Partial cache line writes which do not allocate into the L1 cache.
  • Non-cacheable accesses.
0x44 [61] L1D_CACHE_REFILL_INNER

L1 data cache refill, inner. This event counts any L1 D-cache linefill (as counted by L1D_CACHE_REFILL) which hits in the L2 cache, L3 cache or another core in the cluster.

0x45 [62] L1D_CACHE_REFILL_OUTER

L1 data cache refill, outer. This event counts any L1 D-cache linefill (as counted by L1D_CACHE_REFILL) which does not hit in the L2 cache, L3 cache or another core in the cluster, and instead obtains data from outside the cluster.

0x46 [63] L1D_CACHE_WB_VICTIM L1 data cache write-back, victim
0x47 [64] L1D_CACHE_WB_CLEAN L1 data cache write-back cleaning and coherency
0x48 [65] L1D_CACHE_INVAL L1 data cache invalidate.
0x4C [66] L1D_TLB_REFILL_RD L1 data TLB refill, read.
0x4D [67] L1D_TLB_REFILL_WR L1 data TLB refill, write.
0x4E [69:68] L1D_TLB_RD L1 data TLB access, read.
0x4F [71:70] L1D_TLB_WR L1 data TLB access, write.
0x50 [73:72] L2D_CACHE_RD

L2 data cache access, read. This event counts any read transaction from L1 which looks up in the L2 cache.

Snoops from outside the core are not counted.

0x51 [75:74] L2D_CACHE_WR

L2 data cache access, write. This event counts any write transaction from L1 which looks up in the L2 cache or any write-back from L1 which allocates into the L2 cache.

Snoops from outside the core are not counted.

0x52 [77:76] L2D_CACHE_REFILL_RD

L2 data cache refill, read. This event counts any cacheable read transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions.

0x53 [79:78] L2D_CACHE_REFILL_WR

L2 data cache refill, write. This event counts any write transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted. Transactions such as ReadUnique are not counted as write transactions.

0x56 [81:80] L2D_CACHE_WB_VICTIM L2 data cache write-back, victim.
0x57 [83:82] L2D_CACHE_WB_CLEAN L2 data cache write-back, cleaning and coherency.
0x58 [85:84] L2D_CACHE_INVAL L2 data cache invalidate.
0x5C [86] L2D_TLB_REFILL_RD L2 data or unified TLB refill, read.
0x5D [87] L2D_TLB_REFILL_WR L2 data or unified TLB refill, write.
0x5E [89:88] L2D_TLB_RD L2 data or unified TLB access, read.
0x5F [90] L2D_TLB_WR L2 data or unified TLB access, write.
0x60 [91] BUS_ACCESS_RD

Bus access read. This event counts for every beat of data transferred over the read data channel between the core and the SCU.

0x61 [92] BUS_ACCESS_WR

Bus access write. This event counts for every beat of data transferred over the write data channel between the core and the SCU.

0x66 [94:93] MEM_ACCESS_RD

Data memory access, read. This event counts memory accesses due to load instructions. The following instructions are not counted:

• Instruction fetches.

• Cache maintenance instructions.

• Translation table walks.

• Prefetches.

0x67 [96:95] MEM_ACCESS_WR

Data memory access, write. This event counts memory accesses due to store instructions.

The following instructions are not counted:

• Instruction fetches.

• Cache maintenance instructions.

• Translation table walks.

• Prefetches.

0x68 [98:97] UNALIGNED_LD_SPEC Unaligned access, read
0x69 [100:99] UNALIGNED_ST_SPEC Unaligned access, write
0x6A [103:101] UNALIGNED_LDST_SPEC Unaligned access
0x6C [178] LDREX_SPEC Exclusive operation speculatively executed, LDREX or LDX.
0x6D [180] STREX_PASS_SPEC Exclusive operation speculatively executed, STREX or STX pass.
0x6E [181] STREX_FAIL_SPEC Exclusive operation speculatively executed, STREX or STX fail.
0x6F [182] STREX_SPEC Exclusive operation speculatively executed, STREX or STX.
0x70 [107:104] LD_SPEC Operation speculatively executed, load.
0x71 [111:108] ST_SPEC Operation speculatively executed, store.
0x72 [113:112] LDST_SPEC

Operation speculatively executed, load or store. This event counts the sum of LD_SPEC and ST_SPEC.

0x73 [117:114] DP_SPEC Operation speculatively executed, integer data-processing.
0x74 [121:118] ASE_SPEC Operation speculatively executed, Advanced SIMD instruction.
0x75 [125:122] VFP_SPEC Operation speculatively executed, floating-point instruction.
0x76 [127:126] PC_WRITE_SPEC Operation speculatively executed, software change of the PC.
0x77 [131:128] CRYPTO_SPEC Operation speculatively executed, Cryptographic instruction.
0x78 [133:132] BR_IMMED_SPEC Branch speculatively executed, immediate branch.
0x79 [135:134] BR_RETURN_SPEC Branch speculatively executed, procedure return.
0x7A [175:174] BR_INDIRECT_SPEC Branch speculatively executed, indirect branch.
0x7C [176] ISB_SPEC Barrier speculatively executed, ISB.
0x7D [137:136] DSB_SPEC Barrier speculatively executed, DSB.
0x7E [139:138] DMB_SPEC Barrier speculatively executed, DMB.
0x81 [140] EXC_UNDEF Counts the number of undefined exceptions taken locally.
0x82 [141] EXC_SVC Exception taken locally, Supervisor Call.
0x83 [142] EXC_PABORT Exception taken locally, Instruction Abort.
0x84 [143] EXC_DABORT Exception taken locally, Data Abort and SError.
0x86 [144] EXC_IRQ Exception taken locally, IRQ.
0x87 [145] EXC_FIQ Exception taken locally, FIQ.
0x88 [146] EXC_SMC Exception taken locally, Secure Monitor Call.
0x8A [147] EXC_HVC Exception taken locally, Hypervisor Call.
0x8B [148] EXC_TRAP_PABORT Exception taken, Instruction Abort not taken locally.
0x8C [149] EXC_TRAP_DABORT Exception taken, Data Abort or SError not taken locally.
0x8D [150] EXC_TRAP_OTHER Exception taken, Other traps not taken locally.
0x8E [183] EXC_TRAP_IRQ Exception taken, IRQ not taken locally.
0x8F [184] EXC_TRAP_FIQ Exception taken, FIQ not taken locally.
0x90 [154:151] RC_LD_SPEC Release consistency operation speculatively executed, load-acquire.
0x91 [158:155] RC_ST_SPEC Release consistency operation speculatively executed, store-release.
0xA0 [169] L3_CACHE_RD L3 cache read.
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