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External register access permissions

Whether or not access is permitted to a register depends on:

  • If the core is powered up.
  • The state of the OS Lock and OS Double Lock.
  • The state of External Performance Monitors access disable.
  • The state of the debug authentication inputs to the core.

The behavior is specific to each register and is not described in this document. For a detailed description of these features and their effects on the registers, see the Arm® Architecture Reference Manual Arm®v8, for Arm®v8-A architecture profile.

The register descriptions provided in this manual describe whether each register is read/write or read-only.

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