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CoreLink SSE‑050 Subsystem for Embedded

The Arm® CoreLink™ SSE-050 Subsystem for Embedded is a subsystem that provides a starting point for a product in the Internet of Things (IoT) and embedded market segments.

The SSE-050 subsystem delivers a process and technology agnostic reference, pre-integrated, validated, hardware and software subsystem that can be extended to provide an IoT endpoint system.

The SSE solution consists of hardware, software, and software tools to enable the rapid development of IoT System on Chip (SoC) solutions.

The SSE‑050 Subsystem for Embedded contains the following components:

  • A Cortex®-M3 processor:
    • Bit-banding enables using standard instructions to read or modify individual bits. The default implementation does not include bit banding.
    • Eight MPU regions (optional).
    • NVIC providing deterministic, high-performance interrupt handling with a configurable number of interrupts.
    • Wakeup Interrupt Controller (WIC) with configurable number of WIC lines (optional). This is a latch-based WIC implementation, and not the standard Cortex-M3 WIC. See the Arm® CoreLink™ SSE-050 Subsystem Configuration and Integration Manual for more information.
    • Little-endian memory addressing only (for compatibility with the eFlash cache).

    For more information, see the Arm® Cortex®-M3 Processor Technical Reference Manual.

    The Cortex-M3 processor has a Processor Integration Layer (PIL) to simplify integration of the SSE‑050 Subsystem into a multiprocessor system with a SoC-level CoreSight™ subsystem.

  • Configurable Debug and Trace as either:
    • Standalone system with a Trace Port Interface Unit (TPIU) and an SWJ-DP.
    • Full CoreSight integration over a DAP and the ATB buses.
  • Multilayer AMBA AHB-Lite interconnect:
    • Low-latency interconnect bus matrix.
    • Two AHB-Lite initiator expansion ports for external AHB masters.
    • Two AHB-Lite target expansion ports for external AHB slaves.
    • 11 APB4 target expansion ports (each with 4KB address space) to connect APB peripherals.
  • Memory system, consisting of:
    • Placeholder for eFlash controller and optional cache.
    • Static memory (configurable as one to four 32KB banks) is provided in the example integration layer.
  • Two APB timers:
    • Interrupt generation when the counter reaches 0.
    • Each timer has an TIMERnEXTIN signal that can be used as an enable or external clock.
    • Configurable privileged access mode.

The following figure shows the SSE‑050 Subsystem for Embedded, with other IP, in an example design.

Figure 2-1 SSE-050 Subsystem for Embedded example design


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