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Programmers model

This section describes the programmers model of the System Watchdog.

The Watchdog includes the following two 4KB register frames:

  • Control Frame.
  • Refresh Frame.

Configurable parameters control the base addresses of Control and Refresh frames. These parameters provide the flexibility of arranging these two frames within an 8KB memory map that the following table shows. See Programmers model for the base addresses of these registers in SSE‑123 Subsystem.

The following table shows the Base addresses of Control and Refresh frames.

Table B-19 Base addresses of Control and Refresh frames

Description Start address End address Size
Control Frame 0x0_0000 0x0_0FFF 4KB
Refresh Frame 0x0_1000 0x0_1FFF 4KB

Control Frame registers summary

This section provides a summary of the Control Frame registers.

The following table shows the Control Frame registers summary.

Table B-20 Control Frame registers summary

Offset Name Access Reset value Description
0x000 WCS RW 0x0000_0000 WCS, Watchdog Control and Status register
0x004 - RES0 - Reserved.
0x008 WOR RW 0x0000_0000 WOR, Watchdog Offset register.
0x00c - RES0 - Reserved.
0x010 WCV[31:0] RW 0x0000_0000 WCV, Watchdog Compare Value register
0x014 WCV[63:32] RW 0x0000_0000 -
0x018-0xFC8 - RES0 - Reserved.
0xFCC W_IIDR RO 0x0000_143B W_IIDR, Watchdog Interface Identification register
0xFD0-0xFFC - RO - Reserved.

Refresh Frame registers Summary

This section provides a summary of the Refresh Frame registers.

The following table shows a summary of the Refresh Frame registers.

Table B-21 Refresh Frame registers summary

Offset Name Access Reset value Description
0x000 WRR RW 0x0000_0000 WRR, Watchdog Refresh register.
0x004-0xFC8 - - - Reserved.
0xFCC W_IIDR RO 0x0000_143B W_IIDR, Watchdog Interface Identification register.
0xFD0-0xFFC - RO - Reserved.

Register descriptions

This section describes each System Watchdog register.

All registers are 32‑bit and must be accessed using 32‑bit reads and writes.

WCS, Watchdog Control and Status register

The WCS register is a control and status register for the watchdog. Any write to this register causes an explicit watchdog refresh.

The following table shows the bit assignments.

Table B-22 WCS register bit assignments

Bits Name Access Reset value Function
[31:3] - RAZ/WI - Reserved.
[2:1] Watchdog Signal Status RO 0x0

Indicates the current state of the watchdog signals:

Bit 0WS0 Interrupt INTR[0].
Bit 1WS1 Interrupt INTR[1].
[0] Watchdog Enable RW 0x0

Watchdog enable:

0A write of 0 disables the Watchdog.
1A write of 1 to this bit enables the Watchdog.

A read of these bits indicates the current state of the Watchdog enable.

WOR, Watchdog Offset register

The WOR register is a countdown timer value for the watchdog. Any write to this register causes an explicit watchdog refresh.

The following table shows the bit assignments.

Table B-23 WOR register bit assignments

Bits Name Access Reset value Function
[31:0] WOR RW 0x0000_0000 Holds the 32‑bit countdown timer value.

WCV, Watchdog Compare Value register

The WCV register holds the compare value of the watchdog.

The following table shows the bit assignments.

Table B-24 WCV register bit assignments

Bits Name Access Reset value Function
[63:0] WCV RW 0x0000_0000 Holds the current 64‑bit compare value.

W_IIDR, Watchdog Interface Identification register

The W_IIDR register is an identification register for the watchdog.

The following table shows the bit assignments.

Table B-25 W_IIDR register bit assignments

Bits Name Access Reset value Function
[31:24] ID RO 0x00

Product identifier.

0x00 = System Watchdog.

[23:20] - RO 0x0 Reserved.
[19:16] ARCH RO 0x0 Architecture version, v0.
[15:12] REV RO 0x1

Revision number for the component.

0x1 = r0p1

[11:0] JEPCODE RO 0x43B Arm® JEP106 code.

WRR, Watchdog Refresh register

The WRR register is a refresh register for the Watchdog. Any write to this register causes an explicit watchdog refresh.

The following table shows the bit assignments.

Table B-26 WRR register bit assignments

Bits Name Access Function
[31:0] WRR RW A write to this location causes the Watchdog to refresh and start a new watch period. A read has no effect and returns 0.
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