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Features of SSE-123

The SSE‑123 Example Subsystem provides the following features:

  • A Cortex®‑M23 processor, including Armv8‑M Security Extensions.
  • A single bank of system SRAM.
  • CoreLink™ SIE‑200 System IP for Embedded:
    • AHB5 bus matrix.
    • Memory Protection Controller (MPC).
    • Peripheral Protection Controller (PPC).
    • AHB5 to APB4 bridge.
    • AHB5 to SRAM controller.
  • CoreLink PCK‑600 Power Control Kit:
    • Power Policy Unit (PPU).
    • Clock controller.
    • Low‑Power Distributor Q‑Channel (LPD‑Q).
  • Implementation Defined Attribution Unit (IDAU).
  • Cortex‑M23 processor Wakeup Interrupt Controller (WIC).
  • System Timer and Watchdog.
  • System Control and Security Control Registers.
  • Optional Cortex‑M23 processor Debug components:
    • Embedded Trace Macrocell (ETM).
    • Cross Trigger Interface (CTI).
    • Debug APB interconnect.
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